Renesas Electronics /R7FA6T2BD /PDG /GTDLYCR

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Interpret as GTDLYCR

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)DLLEN 0 (0)DLYRST 0 (0)FRANGE

FRANGE=0, DLLEN=0, DLYRST=0

Description

PWM Output Delay Control Register

Fields

DLLEN

DLL Operation Enable

0 (0): DLL operation disabled

1 (1): DLL operation enabled

DLYRST

PWM Delay Generation Circuit Reset

0 (0): Normal operation

1 (1): Reset

FRANGE

GPT core clock Frequency Range

0 (0): GPT core clock frequency is 115 MHz to 200 MHz

1 (1): GPT core clock frequency is 80 MHz to 120 MHz

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